Field-programmable gate arrays are commonly utilized in designs that require high adaptability due to rapidly and dynamically changing requirements, which would make the high cost of ASICs untenable. These designs typically involve relatively low-volume specialty applications, nascent markets where requirements are still maturing, nascent technologies where capabilities and standards are rapidly evolving, or, in the case of edge AI, a combination of all these factors.

Even with the general advantages that FPGAs have versus ASICs, not all FPGAs are designed equally. Various design considerations and tradeoffs can help a given FPGA solution be more optimized for a specific use case or application. Like most things, the more defined the target use case is, the more optimized the solution can be in terms of performance, power efficiency and form factor.

When designing a solution using FPGAs, many factors come into play. Considerations like the development environment, design tools and support community are all important aspects. However, it all starts with the hardware design. In the world of small FPGA platforms—typically FPGAs with a logic density of about 200k system logic cells (SLCs) or less, especially when targeted at developing edge AI applications—this can be boiled down to how well the design performs in terms of computational power, boot times, power consumption, form factor and security.    

An example of a recently released small FPGA platform targeting embedded edge AI applications is Lattice Semiconductor’s Nexus 2 platform. Given the increased computational requirements of edge AI applications, Nexus 2 not only features enhanced processing and memory subsystems but also increased interconnect capabilities to support the higher data bandwidths required by AI applications, according to the company.